Emerged real-time multi-media applications demand smaller, faster and less power consuming systems than ever before. Nanometer IC fabrication technology provides means to put billion of gates on one chip and operate it with multi GHz frequency under 1V voltage supply. However, current design methods and CAD tools are not capable of supporting such complex system design. Development of new methodologies and tools that allow to cope with System-on-Silicon design is the main target of our current research activities. Our current research is conducted in the following directions:

  1. Research on low-power (low energy) processor architecture
    This project focuses on adaptive macro- and micro-architectural solutions and design techniques capable of exploiting workload characteristics and input data features to reduce access count, voltage supply and active bitwidth of caches, instruction queues, reorder buffers, register files, functional units, etc. without affecting the processor performance.
  2. Lower-Power Arithmetic
    This research encompasses algorithmic/structural transformations for reducing power consumption of ALUs, digital multipliers and multiplier-accumulators. Various adding schemes, multiplication algorithms, pipelining and coding techniques are studied from the switching activity reduction perspective. New schemes for elimination of unnecessary transitions in signed-digit adders and multipliers are being developed. Application of the adaptive bit-width, voltage scaling and input reordering and operand transormation techniques are investigated.
  3. Research on energy-efficient video-processing methods
    With the growing popularity of portable video phones, energy dissipation in video coding/encoding processor becomes a main concern. This project investigates video coding/encoding scheme with data-reusing properties. Our main idea is to enable the hardware to adjust the number of computations/memory accesses to the picture variation and thus decrease energy consumption of the system. By developing such a methodology we expect to reduce the power consumption of the prototype processor by 1/3 without affecting the picture quality and performance. Currently we are engaged in development of data-reusable encoding and decoding schemes, data-driven block characterization, computationally adaptive algorithms for motion estimation, DCT and vector quantization, adaptive memory accessing, memory sharing and data reusing techniques.
  4. Research on event-driven low-energy ubiquitous systems
    This project deals with investigation on new methodologies and platforms for design and development of event-driven reconfigurable systems capable of adjusting their perfomance and energy consumption to the dynamically varying requirements.

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